Invention Grant
- Patent Title: Method and apparatus for inspection and fault analysis
- Patent Title (中): 检查和故障分析的方法和装置
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Application No.: US12164594Application Date: 2008-06-30
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Publication No.: US08090191B2Publication Date: 2012-01-03
- Inventor: Kiyoshi Nikawa
- Applicant: Kiyoshi Nikawa
- Applicant Address: JP Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kanagawa
- Agency: Young & Thompson
- Priority: JP2007-172555 20070629
- Main IPC: G06K9/00
- IPC: G06K9/00

Abstract:
Apparatus for inspection and fault analysis of semiconductor chip includes stage on which to mount LSI chip, and test pattern generator supplying test pattern via stage to LSI chip. Apparatus also includes optical system having function of modulating laser beam. This optical system operates so that LSI chip is scanned and illuminated by modulated laser beam. IR-OBIRCH controller performs image processing of taking out only signal of preset frequency from signal from LSI chip via lock-in amplifier, and correlates signal taken out with scanning points. Lock-in amplifier is adapted to take out only signal of preset frequency from signal from LSI chip. A display section displays image based on image signal from IR-OBIRCH controller which confirms presence or absence of abnormal current route in LSI chip based on image signal.
Public/Granted literature
- US20090003685A1 METHOD AND APPARATUS FOR INSPECTION AND FAULT ANALYSIS Public/Granted day:2009-01-01
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