In response to an input signal, in a first delay line, a delay amount is added to a phase of the input signal by each delay unit. In a DLL circuit, in response to an external signal that can be externally switched to a signal different in frequency is accepted, in a second delay line, a delay amount is added to the phase of the external signal by each delay unit. The phase of a delay signal delayed by all delay units of the second delay line and the phase of the external signal to which no delay amount added are compared to output a phase difference. A control voltage value that is a value for synchronizing the delay signal to be compared by the phase comparator and is generated from the phase difference output from the phase comparator is input to each of the delay units.