Invention Grant
US08088668B2 Method for manufacturing capacitor lower electrodes of semiconductor memory
有权
制造半导体存储器的电容器下电极的方法
- Patent Title: Method for manufacturing capacitor lower electrodes of semiconductor memory
- Patent Title (中): 制造半导体存储器的电容器下电极的方法
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Application No.: US12700088Application Date: 2010-02-04
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Publication No.: US08088668B2Publication Date: 2012-01-03
- Inventor: Shin Bin Huang , Chung-Yi Chang , Jung-Hung Wang
- Applicant: Shin Bin Huang , Chung-Yi Chang , Jung-Hung Wang
- Applicant Address: TW Taoyuan County
- Assignee: Inotera Memories, Inc.
- Current Assignee: Inotera Memories, Inc.
- Current Assignee Address: TW Taoyuan County
- Agency: Rosenberg, Klein & Lee
- Priority: TW98133199A 20090930
- Main IPC: H01L21/20
- IPC: H01L21/20

Abstract:
A method for manufacturing capacitor lower electrodes of a semiconductor memory firstly forms a first stacked structure over a semiconductor substrate which has a plurality of conductive plugs. Then a second stacked structure is formed on the first stacked structure; furthermore, a plurality of trenches extending from a top surface of the second stacked structure to a bottom surface of the first stacked structure are formed and expose the conducting plugs; finally, conductive metal materials and solid conducting cylindrical structures are deposited in the trenches in turn, and the conductive metal materials contact with the conductive plugs and the conducting cylindrical structures. Each conducting cylindrical structure is a capacitor lower electrode. Accordingly, the present invention can increase the supporting stress of the capacitor lower electrodes and further reduce the difficulty in disposing of capacitor upper electrodes and capacitor dielectric layers outside the capacitor lower electrodes.
Public/Granted literature
- US20110076828A1 METHOD FOR MANUFACTURING CAPACITOR LOWER ELECTRODES OF SEMICONDUCTOR MEMORY Public/Granted day:2011-03-31
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