Invention Grant
- Patent Title: Method of fabricating chip package
- Patent Title (中): 制造芯片封装的方法
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Application No.: US12506245Application Date: 2009-07-20
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Publication No.: US08088650B2Publication Date: 2012-01-03
- Inventor: Yong-Chao Qiao , Jie-Hung Chiou , Yan-Yi Wu
- Applicant: Yong-Chao Qiao , Jie-Hung Chiou , Yan-Yi Wu
- Applicant Address: BM Hamilton
- Assignee: ChipMOS Technologies (Bermuda) Ltd.
- Current Assignee: ChipMOS Technologies (Bermuda) Ltd.
- Current Assignee Address: BM Hamilton
- Agency: Jianq Chyun IP Office
- Priority: CN200710087671 20070313
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
A method of fabricating a chip package is provided. A thin metal plate having a first protrusion part, a second protrusion part and a plurality of third protrusion parts are provided. A chip is disposed on the thin metal plate, and a plurality of bonding wires for electrically connecting the chip to the second protrusion part and the second protrusion part to the third protrusion parts is formed. An upper encapsulant and a lower encapsulant are formed on the upper surface and the lower surface of the thin metal plate respectively. The lower encapsulant has a plurality of recesses for exposing a portion of the thin metal plate at locations where the first protrusion part, the second protrusion part and the third protrusion parts are connected to one another. Finally, the thin metal plate is etched by using the lower encapsulant as an etching mask.
Public/Granted literature
- US20090280603A1 METHOD OF FABRICATING CHIP PACKAGE Public/Granted day:2009-11-12
Information query
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