The present invention provides a circuit for controlling a column-command address corresponding to a specific column of a DRAM array. The circuit includes a control unit and a FIFO register. The control unit determines a period number, and synchronously produces an input pointer and an output pointer, wherein the output pointer is lagged behind the input pointer by the period number. The FIFO register utilizes the input pointer to store the column-command address, and utilizes the output pointer to output the column-command address.