Invention Grant
- Patent Title: Silicon substrate for package
- Patent Title (中): 硅衬底封装
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Application No.: US12257626Application Date: 2008-10-24
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Publication No.: US07989927B2Publication Date: 2011-08-02
- Inventor: Akinori Shiraishi , Kei Murayama , Yuichi Taguchi , Masahiro Sunohara , Mitsutoshi Higashi
- Applicant: Akinori Shiraishi , Kei Murayama , Yuichi Taguchi , Masahiro Sunohara , Mitsutoshi Higashi
- Applicant Address: JP Nagano-shi
- Assignee: Shinko Electric Industries Co., Ltd.
- Current Assignee: Shinko Electric Industries Co., Ltd.
- Current Assignee Address: JP Nagano-shi
- Agency: Rankin, Hill & Clark LLP
- Priority: JP2007-280695 20071029
- Main IPC: H01L23/49
- IPC: H01L23/49

Abstract:
In a silicon substrate for a package, a through electrode is provided with which a through hole passing through from a bottom surface of a cavity for accommodating a chip of an electronic device to a back surface of the substrate is filled. An end part of the through electrode in the bottom surface side of the cavity has a connection part to a wiring that forms an electric circuit including the chip of the electronic device. The silicon substrate for a package is characterized in that (1) a thin film wiring is included as the wiring and the connection part is reinforced by a conductor connected to the thin film wiring and/or (2) a wire bonding part is included as the wiring and the connection part is formed by wire bonding the end part of the through electrode in the bottom surface side of the cavity.
Public/Granted literature
- US20090108411A1 SILICON SUBSTRATE FOR PACKAGE Public/Granted day:2009-04-30
Information query
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