Invention Grant
US07989352B2 Technique for reducing plasma-induced etch damage during the formation of vias in interlayer dielectrics
有权
在层间电介质形成通孔期间降低等离子体诱导蚀刻损伤的技术
- Patent Title: Technique for reducing plasma-induced etch damage during the formation of vias in interlayer dielectrics
- Patent Title (中): 在层间电介质形成通孔期间降低等离子体诱导蚀刻损伤的技术
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Application No.: US11696226Application Date: 2007-04-04
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Publication No.: US07989352B2Publication Date: 2011-08-02
- Inventor: Frank Feustel , Kai Frohberg , Thomas Werner
- Applicant: Frank Feustel , Kai Frohberg , Thomas Werner
- Applicant Address: US TX Austin
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US TX Austin
- Agency: Williams, Morgan & Amerson, P.C.
- Priority: DE102006041004 20060831
- Main IPC: H01L21/302
- IPC: H01L21/302 ; H01L21/461
Abstract:
By forming a conductive material within an etch mask for an anisotropic etch process for patterning openings, such as vias, in a dielectric layer of a metallization structure, the probability for arcing events may be reduced, since excess charge may be laterally distributed. For example, an additional sacrificial conductive layer may be formed or an anti-reflecting coating (ARC) may be provided in the form of a conductive material in order to obtain the lateral charge distribution.
Public/Granted literature
- US20080057705A1 TECHNIQUE FOR REDUCING PLASMA-INDUCED ETCH DAMAGE DURING THE FORMATION OF VIAS IN INTERLAYER DIELECTRICS Public/Granted day:2008-03-06
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