Invention Grant
- Patent Title: Dual damascence copper process using a selected mask
- Patent Title (中): 使用选择的掩模的双重防腐铜工艺
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Application No.: US11539614Application Date: 2006-10-06
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Publication No.: US07989341B2Publication Date: 2011-08-02
- Inventor: Fan Chung Tseng , Chi Hsi Wu , Wei Ting Chien
- Applicant: Fan Chung Tseng , Chi Hsi Wu , Wei Ting Chien
- Applicant Address: CN Shanghai
- Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
- Current Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
- Current Assignee Address: CN Shanghai
- Agency: Kilpatrick Townsend and Stockton LLP
- Priority: CN200610023301 20060113
- Main IPC: H01L21/4763
- IPC: H01L21/4763

Abstract:
A method for creating a dual damascene structure while using only one lithography and masking step. Conventional dual damascene structures utilize two lithography steps: one to mask and expose the via, and a second step to mask and expose the trench interconnection. The novel method for creating a dual damascene structure allows for a smaller number of processing steps, thus reducing the processing time needed to complete the dual damascene structure. In addition, a lower number of masks may be needed. The exemplary mask or reticle used within the process incorporates different regions possessing different transmission rates. During the exposing step, light from an exposing source passes through the mask to expose a portion of the photoresist layer on top of the wafer. Depending on the transmission rate of the different regions, different thickness of the photoresist layer are exposed and later removed by a developing solution, which allows a subsequent etch process to remove portions of both the dielectric layer and photoresist layer to create a dual damascene structure.
Public/Granted literature
- US20080020565A1 Dual Damascene Copper Process Using a Selected Mask Public/Granted day:2008-01-24
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