Invention Grant
US07989292B2 Method of fabricating a semiconductor device with a channel formed in a vertical direction
有权
制造具有在垂直方向上形成的通道的半导体器件的方法
- Patent Title: Method of fabricating a semiconductor device with a channel formed in a vertical direction
- Patent Title (中): 制造具有在垂直方向上形成的通道的半导体器件的方法
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Application No.: US12334324Application Date: 2008-12-12
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Publication No.: US07989292B2Publication Date: 2011-08-02
- Inventor: Sang-Hoon Cho , Yun-Seok Cho , Myung-Ok Kim , Sang-Hoon Park , Young-Kyun Jung
- Applicant: Sang-Hoon Cho , Yun-Seok Cho , Myung-Ok Kim , Sang-Hoon Park , Young-Kyun Jung
- Applicant Address: KR Icheon-si, Gyeonggi-do
- Assignee: Hynix Semiconductor Inc.
- Current Assignee: Hynix Semiconductor Inc.
- Current Assignee Address: KR Icheon-si, Gyeonggi-do
- Agency: Lowe Hauptman Ham & Berner LLP
- Priority: KR10-2008-0030166 20080401
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
In a method of fabricating a semiconductor device on a substrate which includes a plurality of pillar patterns, an impurity region between adjacent pillar patterns, a gate electrode on each pillar pattern, a first capping layer covering the gate electrode, and a separation layer covering the first capping layer between the gate electrodes of adjacent pillar patterns, the first capping layer is removed except for a portion contacting the separation layer, a sacrificial layer is formed to cover the gate electrode, a second capping layer is formed on sidewalls of each pillar pattern, the sacrificial layer is removed and a word line connecting the gate electrodes of the adjacent pillar patterns is formed. In the manufactured device, the first capping layer isolates the impurity region from the word line and the second capping region prevents the sidewalls of the respective pillar pattern from being exposed.
Public/Granted literature
- US20090242971A1 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME Public/Granted day:2009-10-01
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