Invention Grant
- Patent Title: Semiconductor device and method of forming three-dimensional vertically oriented integrated capacitors
- Patent Title (中): 形成三维垂直取向的集成电容器的半导体器件和方法
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Application No.: US12404134Application Date: 2009-03-13
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Publication No.: US07989270B2Publication Date: 2011-08-02
- Inventor: Rui Huang , Heap Hoe Kuan , Yaojian Lin , Seng Guan Chow
- Applicant: Rui Huang , Heap Hoe Kuan , Yaojian Lin , Seng Guan Chow
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC, Ltd.
- Current Assignee: STATS ChipPAC, Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group
- Agent Robert D. Atkins
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/20

Abstract:
A semiconductor device is made by forming a plurality of conductive pillars vertically over a temporary carrier. A conformal insulating layer is formed over the conductive pillars. A conformal conductive layer is formed over the conformal insulating layer. A first conductive pillar, conformal insulating layer, and conformal conductive layer constitute a vertically oriented integrated capacitor. A semiconductor die or component is mounted over the carrier. An encapsulant is deposited over the semiconductor die or component and around the conformal conductive layer. A first interconnect structure is formed over a first side of the encapsulant. The first interconnect structure includes an integrated passive device. The first interconnect structure is electrically connected to the semiconductor die or component and vertically oriented integrated capacitor. The carrier is removed. A second interconnect structure is formed over a second side of the encapsulant opposite the first side of the encapsulant.
Public/Granted literature
- US20100230806A1 Semiconductor Device and Method of Forming Three-Dimensional Vertically Oriented Integrated Capacitors Public/Granted day:2010-09-16
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