Invention Grant
US07989232B2 Method of using electrical test structure for semiconductor trench depth monitor
有权
半导体沟槽深度监测仪使用电气测试结构的方法
- Patent Title: Method of using electrical test structure for semiconductor trench depth monitor
- Patent Title (中): 半导体沟槽深度监测仪使用电气测试结构的方法
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Application No.: US11531103Application Date: 2006-09-12
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Publication No.: US07989232B2Publication Date: 2011-08-02
- Inventor: Qingfeng Wang , Sameer P. Pendharkar , Binghua Hu
- Applicant: Qingfeng Wang , Sameer P. Pendharkar , Binghua Hu
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Warren L. Franz; Wade J. Brady, III; Frederick J. Telecky, Jr.
- Main IPC: H01L21/66
- IPC: H01L21/66 ; H01L27/07

Abstract:
Embodiments provide a method and device for electrically monitoring trench depths in semiconductor devices. To electrically measure a trench depth, a pinch resistor can be formed in a deep well region on a semiconductor substrate. A trench can then be formed in the pinch resistor. The trench depth can be determined by an electrical test of the pinch resistor. The disclosed method and device can provide statistical data analysis across a wafer and can be implemented in production scribe lanes as a process monitor. The disclosed method can also be useful for determining device performance of LDMOS transistors. The on-state resistance (Rdson) of the LDMOS transistors can be correlated to the electrical measurement of the trench depth.
Public/Granted literature
- US20080085569A1 METHOD OF USING ELECTRICAL TEST STRUCTURE FOR SEMICONDUCTOR TRENCH DEPTH MONITOR Public/Granted day:2008-04-10
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