Invention Grant
US07975196B2 Resynchronization memory in series/parallel with control/data scan cells
有权
与控制/数据扫描单元串并联的再同步存储器
- Patent Title: Resynchronization memory in series/parallel with control/data scan cells
- Patent Title (中): 与控制/数据扫描单元串并联的再同步存储器
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Application No.: US13012242Application Date: 2011-01-24
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Publication No.: US07975196B2Publication Date: 2011-07-05
- Inventor: Lee D. Whetsel
- Applicant: Lee D. Whetsel
- Applicant Address: US TX Dallas
- Assignee: Texas Instruments Incorporated
- Current Assignee: Texas Instruments Incorporated
- Current Assignee Address: US TX Dallas
- Agent Lawrence J. Bassuk; W. James Brady; Frederick J. Telecky, Jr.
- Main IPC: G01R31/28
- IPC: G01R31/28

Abstract:
An integrated circuit or circuit board includes functional circuitry and a scan path. The scan path includes a test data input lead, a test data output lead, a multiplexer, and scan cells. A dedicated scan cell has a functional data output separate from a test data output. Shared scan cells each have a combined output for functional data and test data. The shared scan cells are coupled in series. The test data input of the first shared scan cell is connected to the test data output of the dedicated scan cell. The combined output of one shared scan cell is coupled to the test data input lead of another shared scan cell. The multiplexer has an input coupled to the test data output, an input connected to the combined output lead of the last shared scan cell in the series, and an output connected in the scan path.
Public/Granted literature
- US20110119543A1 BOUNDARY SCAN PATH METHOD AND SYSTEM WITH FUNCTIONAL AND NON-FUNCTIONAL SCAN CELL Public/Granted day:2011-05-19
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