Invention Grant
- Patent Title: Adaptive calibration for digital phase-locked loops
- Patent Title (中): 数字锁相环的自适应校准
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Application No.: US12233400Application Date: 2008-09-18
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Publication No.: US07974807B2Publication Date: 2011-07-05
- Inventor: Jifeng Geng , Daniel F. Filipovic , Christos Komninakis
- Applicant: Jifeng Geng , Daniel F. Filipovic , Christos Komninakis
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agent Jonathan T. Velasco
- Main IPC: G06F19/00
- IPC: G06F19/00

Abstract:
Techniques for adaptively calibrating a TDC output signal in a digital phase-locked loop (DPLL). In an exemplary embodiment, a calibration factor multiplied to the TDC output signal is adaptively adjusted to minimize a magnitude function of a phase comparator output signal of the DPLL. In an exemplary embodiment, the calibration factor may be adjusted using an exemplary embodiment of the least-mean squares (LMS) algorithm. Further techniques for simplifying the adaptive algorithm for hardware implementation are described.
Public/Granted literature
- US20100066421A1 ADAPTIVE CALIBRATION FOR DIGITAL PHASE-LOCKED LOOPS Public/Granted day:2010-03-18
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