Invention Grant
- Patent Title: Supply-regulated phase-locked loop (PLL) and method of using
- Patent Title (中): 供电调节锁相环(PLL)及其使用方法
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Application No.: US12430104Application Date: 2009-04-26
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Publication No.: US07973612B2Publication Date: 2011-07-05
- Inventor: Ashwin Raghunathan , Marzio Pedrali-Noy
- Applicant: Ashwin Raghunathan , Marzio Pedrali-Noy
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agent Eric Ho
- Main IPC: H03L7/099
- IPC: H03L7/099

Abstract:
A supply-regulated Phase-locked loop (PLL) is provided. The PLL comprises a supply-regulating loop, a voltage-controlled oscillator (VCO), and a programmable decoupling capacitor array for the VCO. The capacitance of the VCO decoupling capacitor array is adjustable to be equal to N times CUNIT, where N is the current value of a multiplication factor of a divide-by-N circuit and CUNIT is a unit capacitance characterized for a processing technology chosen for fabricating the decoupling capacitor array. When the PLL switches from one frequency band to another, a higher-order pole introduced by the VCO decoupling capacitor tracks the PLL reference frequency, thus improving the PLL operational stability.
Public/Granted literature
- US20100271140A1 Supply-Regulated Phase-Locked Loop (PLL) and Method of Using Public/Granted day:2010-10-28
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