A sample-and-hold circuit (100) is provided that that includes a sample-and-hold switch (125), an integrator circuit (180) designed to generate an output voltage (VOUT) signal, and a bias voltage (VBIAS) source (185). The sample-and-hold switch (125) incldues a first switch (130), a second switch (140), and a third switch (150). The first switch (130) has a first gate (132), a first source (134) and a first drain (134), the second switch (140) has a second gate (142), a second source (144) electrically coupled to a bulk region (147), and a second drain (146), and the third switch (150) has a third gate (152), a third drain (154), and a third source (156) coupled to the first source (136). The integrator circuit (180) includes an output operational amplifier (170) having an inverting input (V−) (172) coupled to the second drain (146) and a non-inverting input (V+). The bias voltage (VBIAS) source (185) applies a bias voltage (VBIAS) to the third drain and the non-inverting input (V+) to drive a gate-to-source voltage (VGS) of the second switch (140) to an optimum negative value that reduces a sub-threshold leakage current (IDS) and a Gate Induced Drain Lowering (GIDL) leakage current in the second switch (140), and to drive a drain-to-source voltage (VDS) of the second switch (140) is biased at a low value equal to an offset voltage (VOFFSET) of the output operational amplifier (170) to minimize a drain-to-bulk current (IDB) in the second switch (140).