Invention Grant
- Patent Title: Method and apparatus for estimating resistance and capacitance of metal interconnects
- Patent Title (中): 用于估计金属互连的电阻和电容的方法和装置
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Application No.: US11951491Application Date: 2007-12-06
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Publication No.: US07973541B2Publication Date: 2011-07-05
- Inventor: Jayakannan Jayapalan , David Bang , Yang Du
- Applicant: Jayakannan Jayapalan , David Bang , Yang Du
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agent Donald C. Kordich
- Main IPC: G01R27/26
- IPC: G01R27/26

Abstract:
Techniques for estimating resistance and capacitance of metal interconnects are described. An apparatus may include an interconnect, a set of pads, a set of isolation circuits, and a test circuit. The set of pads may be coupled to the interconnect and used for simultaneously applying a current through the interconnect and measuring a voltage across the interconnect. The current and voltage may be used to estimate the resistance of the interconnect. The test circuit may charge and discharge the interconnect to estimate the capacitance of the interconnect. The isolation circuits may isolate the pads from the interconnect when the test circuit charges and discharges the interconnect. The apparatus may further include another interconnect, another set of pads, and another set of isolation circuits that may be coupled in a mirror manner. Resistance and/or capacitance mismatch between the two interconnects may be accurately estimated.
Public/Granted literature
- US20090146681A1 METHOD AND APPARATUS FOR ESTIMATING RESISTANCE AND CAPACITANCE OF METAL INTERCONNECTS Public/Granted day:2009-06-11
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