Invention Grant
- Patent Title: Method for manufacturing a wire structure of a semiconductor device
- Patent Title (中): 半导体器件的线结构的制造方法
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Application No.: US12491886Application Date: 2009-06-25
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Publication No.: US07972956B2Publication Date: 2011-07-05
- Inventor: Chun Soo Kang , Jeon Kyu Lee
- Applicant: Chun Soo Kang , Jeon Kyu Lee
- Applicant Address: KR Icheon-si
- Assignee: Hynix Semiconductor Inc.
- Current Assignee: Hynix Semiconductor Inc.
- Current Assignee Address: KR Icheon-si
- Agency: Marshall, Gerstein & Borun LLP
- Priority: KR10-2008-0134832 20081226
- Main IPC: H01L21/4763
- IPC: H01L21/4763

Abstract:
A wire structure of a semiconductor device capable of ensuring a process margin for bit line patterning in a 6F2 cell layout of a semiconductor device, and a method for manufacturing the same.
Public/Granted literature
- US20100164114A1 Wire Structure of Semiconductor Device and Method for Manufacturing the Same Public/Granted day:2010-07-01
Information query
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