Invention Grant
- Patent Title: Method of manufacturing a wafer including providing electrical conductors isolated from circuitry
- Patent Title (中): 制造晶片的方法，包括提供与电路隔离的电导体
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Application No.: US12575586Application Date: 2009-10-08
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Publication No.: US07972902B2Publication Date: 2011-07-05
- Inventor: Sunpil Youn , Seok-Chan Lee
- Applicant: Sunpil Youn , Seok-Chan Lee
- Applicant Address: KR Maetan-dong, Yeongtong-gu, Suwon-si, Gyeonggi-do
- Assignee: Samsung Electronics Co., Ltd.
- Current Assignee: Samsung Electronics Co., Ltd.
- Current Assignee Address: KR Maetan-dong, Yeongtong-gu, Suwon-si, Gyeonggi-do
- Agency: Muir Patent Consulting, PLLC
- Main IPC: H01L21/44
- IPC: H01L21/44
Abstract:
Conductive lines are formed on a wafer containing multiple circuits. The conductive lines are isolated from the circuits formed within the wafer. Chips are mounted on the wafer and have their chip pads connected to the conductive lines of the wafer. The wafer may then be protected with a packaging resin and singulated.
Public/Granted literature
- US20100019397A1 ELECTRICAL CONNECTIONS FOR MULTICHIP MODULES Public/Granted day:2010-01-28
Information query
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