Invention Grant
US07958463B2 Computer automated method for manufacturing an integrated circuit pattern layout
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用于制造集成电路图案布局的计算机自动化方法
- Patent Title: Computer automated method for manufacturing an integrated circuit pattern layout
- Patent Title (中): 用于制造集成电路图案布局的计算机自动化方法
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Application No.: US12242832Application Date: 2008-09-30
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Publication No.: US07958463B2Publication Date: 2011-06-07
- Inventor: Atsuhiko Ikeuchi
- Applicant: Atsuhiko Ikeuchi
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: DLA Piper LLP (US)
- Priority: JPP2004-318427 20041101
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
A computer automated method for designing an integrated circuit includes placing a plurality of marks on each of contours of a plurality of patterns allocated in a chip area; dividing the marks into a plurality of groups so that the adjacent marks are merged in a same group; determining one of the groups as a candidate hot spot based on a total number of marks included in each of the groups; and modifying the corresponding pattern in the candidate hot spot.
Public/Granted literature
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