Invention Grant
US07958333B2 Processor with memory access stage adapted to fetch an instruction of a thread when no memory access operation is detected
有权
具有存储器访问级的处理器，其适于在没有检测到存储器访问操作时获取线程的指令
- Patent Title: Processor with memory access stage adapted to fetch an instruction of a thread when no memory access operation is detected
- Patent Title (中): 具有存储器访问级的处理器，其适于在没有检测到存储器访问操作时获取线程的指令
-
Application No.: US11755119Application Date: 2007-05-30
-
Publication No.: US07958333B2Publication Date: 2011-06-07
- Inventor: Michael David May
- Applicant: Michael David May
- Applicant Address: GB London
- Assignee: XMOS Ltd.
- Current Assignee: XMOS Ltd.
- Current Assignee Address: GB London
- Agency: Sughrue Mion, PLLC
- Main IPC: G06F9/30
- IPC: G06F9/30 ; G06F9/40 ; G06F13/00 ; G06F13/28 ; G06F3/00
Abstract:
A processor and method for executing threads. The processor comprises multiple instruction buffers, each for buffering the instructions of a respective associated thread, and an instruction issue stage for issuing instructions from the instruction buffers to a memory access stage. The memory access stage includes logic adapted to detect whether a memory access operation is defined in each issued instruction, and to fetch another instruction if no memory access operation is detected.
Public/Granted literature
- US20080301409A1 SCHEDULING THREADS IN A PROCESSOR Public/Granted day:2008-12-04
Information query
