Invention Grant
US07957210B2 Variable delay circuit, memory control circuit, delay amount setting apparatus, delay amount setting method and computer-readable recording medium in which delay amount setting program is recorded
失效
可变延迟电路，存储器控制电路，延迟量设定装置，延迟量设定方法以及记录有延迟量设定程序的计算机可读记录介质
- Patent Title: Variable delay circuit, memory control circuit, delay amount setting apparatus, delay amount setting method and computer-readable recording medium in which delay amount setting program is recorded
- Patent Title (中): 可变延迟电路，存储器控制电路，延迟量设定装置，延迟量设定方法以及记录有延迟量设定程序的计算机可读记录介质
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Application No.: US12195914Application Date: 2008-08-21
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Publication No.: US07957210B2Publication Date: 2011-06-07
- Inventor: Manabu Yamazaki
- Applicant: Manabu Yamazaki
- Applicant Address: JP Kawasaki
- Assignee: Fujitsu Limited
- Current Assignee: Fujitsu Limited
- Current Assignee Address: JP Kawasaki
- Agency: Fujitsu Patent Center
- Priority: JP2007-300818 20071120
- Main IPC: G11C7/00
- IPC: G11C7/00
Abstract:
A variable delay circuit being able to change a delay amount from when a signal is inputted to when the signal is outputted has a first delay section delaying the signal by a first delay amount, a second delay section delaying the signal by a second delay amount greater than the first delay amount, and a delay amount selector selecting a signal route where the delay amount is a sum of the first delay amount and the second delay amount when the delay amount exceeds a maximum delay amount delayable by the first delay amount section. The delay amount from when a signal is inputted to when the signal is outputted can be set in a wide range, while suppressing the circuit scale.
Public/Granted literature
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