Invention Grant
- Patent Title: Read and volatile NV standby disturb
- Patent Title (中): 读取和挥发NV备用打扰
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Application No.: US12006225Application Date: 2007-12-31
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Publication No.: US07957192B2Publication Date: 2011-06-07
- Inventor: Andreas Scade , Stefan Guenther , Jeong-Mo Hwang
- Applicant: Andreas Scade , Stefan Guenther , Jeong-Mo Hwang
- Applicant Address: US CA San Jose
- Assignee: Cypress Semiconductor Corporation
- Current Assignee: Cypress Semiconductor Corporation
- Current Assignee Address: US CA San Jose
- Main IPC: G11C11/34
- IPC: G11C11/34
Abstract:
A method of operating a nonvolatile memory circuit having a plurality of transistors arranged in series between a voltage/current source node and recall sink node includes asserting a gate bias on an isolation transistor between the source node and a charge storage transistor during nonvolatile STANDBY.
Public/Granted literature
- US20090168517A1 Read and volatile NV standby disturb Public/Granted day:2009-07-02
Information query
