Invention Grant
US07957188B2 Structures and methods of trimming threshold voltage of a flash EEPROM memory
有权
微调EEPROM存储器阈值电压的结构和方法
- Patent Title: Structures and methods of trimming threshold voltage of a flash EEPROM memory
- Patent Title (中): 微调EEPROM存储器阈值电压的结构和方法
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Application No.: US12613124Application Date: 2009-11-05
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Publication No.: US07957188B2Publication Date: 2011-06-07
- Inventor: Lee Z. Wang , Jui-Hung Huang
- Applicant: Lee Z. Wang , Jui-Hung Huang
- Applicant Address: TW Hsinchu
- Assignee: FS Semiconductor Corp., Ltd.
- Current Assignee: FS Semiconductor Corp., Ltd.
- Current Assignee Address: TW Hsinchu
- Agency: Muncy, Geissler, Olds & Lowe, PLLC
- Main IPC: G11C16/00
- IPC: G11C16/00

Abstract:
A method of trimming FET NVM cells in Multi-Level-Cell (MLC) operation is provided. The method comprises (a) applying a first voltage and a second voltage to a control gate and a bulk of the over-programmed FET NVM cell, respectively; and (b) applying a signal to a drain of the over-programmed FET NVM cell for a time period to produce a limited threshold voltage reduction; wherein polarities of the first voltage and the second voltage are opposite to that of the signal. Thus, the charge placement in the storing material could be precisely controlled within a small range of charge state and produce a multi-bits/cell of higher digital storage density.
Public/Granted literature
- US20110103144A1 STRUCTURES AND METHODS OF TRIMMING THRESHOLD VOLTAGE OF A FLASH EEPROM MEMORY Public/Granted day:2011-05-05
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