A semiconductor memory device includes a first inverter ad a second inverter, a first power supply control circuit, and a second power supply control circuit. The first and second inverters constitute a memory cell and each have an input terminal and an output terminal connected crosswise to an output terminal and an input terminal, respectively, of the other. The first power supply control circuit supplies a first voltage to the first inverter. The second power supply control circuit supplies a second voltage to the second inverter. The first and second power supply control circuits control the first and second voltages, respectively, supplied to the first and second inverters in a selected memory cell for a writing operation in accordance with write data.