Invention Grant
- Patent Title: Reducing resistivity in interconnect structures of integrated circuits
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Application No.: US12690796Application Date: 2010-01-20
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Publication No.: US07956465B2Publication Date: 2011-06-07
- Inventor: Cheng-Lin Huang
- Applicant: Cheng-Lin Huang
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Slater & Matsil, L.L.P.
- Main IPC: H01L23/52
- IPC: H01L23/52
Abstract:
An integrated circuit structure having improved resistivity and a method for forming the same are provided. The integrated circuit structure includes a dielectric layer, an opening in the dielectric layer, an oxide-based barrier layer directly on sidewalls of the opening, and conductive materials filling the remaining portion of the opening.
Public/Granted literature
- US20100171220A1 Reducing Resistivity in Interconnect Structures of Integrated Circuits Public/Granted day:2010-07-08
Information query
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