Invention Grant
- Patent Title: Semiconductor device and wiring structure of triple-layer
- Patent Title (中): 半导体器件和三层布线结构
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Application No.: US11438295Application Date: 2006-05-23
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Publication No.: US07956362B2Publication Date: 2011-06-07
- Inventor: Shunpei Yamazaki
- Applicant: Shunpei Yamazaki
- Applicant Address: JP Kanagawa-ken
- Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee Address: JP Kanagawa-ken
- Agency: Nixon Peabody LLP
- Agent Jeffrey L. Costella
- Priority: JP10-333623 19981125
- Main IPC: H01L29/04
- IPC: H01L29/04 ; H01L27/01

Abstract:
A multi-layered gate electrode of a crystalline TFT is constructed as a clad structure formed by deposition of a first gate electrode, a second gate electrode and a third gate electrode, to thereby to enhance the thermal resistance of the gate electrode. Additionally, an n-channel TFT is formed by selective doping to form a low-concentration impunty region which adjoins a channel forming region, and a sub-region overlapped by the gate electrode and a sub-region not overlapped by the gate electrode, to also mitigate a high electric field near the drain of the TFT and to simultaneously prevent the OFF current of the TFT from increasing.
Public/Granted literature
- US20060208258A1 Semiconductor device, and method of fabricating the same Public/Granted day:2006-09-21
Information query
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