Invention Grant
- Patent Title: Method of fabricating ultra-deep vias and three-dimensional integrated circuits using ultra-deep vias
- Patent Title (中): 使用超深通孔制造超深通孔和三维集成电路的方法
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Application No.: US12540457Application Date: 2009-08-13
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Publication No.: US07955967B2Publication Date: 2011-06-07
- Inventor: Douglas C. La Tulipe, Jr. , Mark Todhunter Robson
- Applicant: Douglas C. La Tulipe, Jr. , Mark Todhunter Robson
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Schmeiser, Olsen & Watts
- Agent Louis J. Percello
- Main IPC: H01L21/4763
- IPC: H01L21/4763

Abstract:
A method of forming a high aspect ratio via opening through multiple dielectric layers, a high aspect ratio electrically conductive via, methods of forming three-dimension integrated circuits, and three-dimensional integrated circuits. The methods include forming a stack of at least four dielectric layers and etching the first and third dielectric layers with processes selective to the second and fourth dielectric layers, etching the second and third dielectric layers with processes selective to the first and second dielectric layers. Advantageously the process used to etch the third dielectric layer is not substantially selective to the first dielectric layer.
Public/Granted literature
- US20110097870A1 METHOD OF FABRICATING ULTRA-DEEP VIAS AND THREE-DIMENSIONAL INTEGRATED CIRCUITS USING ULTRA-DEEP VIAS Public/Granted day:2011-04-28
Information query
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