Invention Grant
- Patent Title: Using crack arrestor for inhibiting damage from dicing and chip packaging interaction failures in back end of line structures
- Patent Title (中): 使用防裂器来抑制线结构后端的切割和芯片封装相互作用故障的损坏
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Application No.: US11746684Application Date: 2007-05-10
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Publication No.: US07955955B2Publication Date: 2011-06-07
- Inventor: Michael W. Lane , Xiao Hu Liu , Thomas M. Shaw , Mukta G. Farooq , Robert Hannon , Ian D. W. Melville
- Applicant: Michael W. Lane , Xiao Hu Liu , Thomas M. Shaw , Mukta G. Farooq , Robert Hannon , Ian D. W. Melville
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agent Graham S. Jones, II; Louis J. Percello; Robert M. Trepp
- Main IPC: H01L21/301
- IPC: H01L21/301

Abstract:
A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep Isolation Trench (UDIT) is cut in the top surface of the chip extending down therein between the perimeter and the barrier. A ILD structure with low-k pSICOH dielectric and hard mask layers is formed over the substrate prior to forming the barrier and the UDIT. The ILD structure interconnection structures can be recessed down to the substrate aside from the UDIT.
Public/Granted literature
- US20080277765A1 INHIBITING DAMAGE FROM DICING AND CHIP PACKAGING INTERACTION FAILURES IN BACK END OF LINE STRUCTURES Public/Granted day:2008-11-13
Information query
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