Invention Grant
US07955955B2 Using crack arrestor for inhibiting damage from dicing and chip packaging interaction failures in back end of line structures 有权
使用防裂器来抑制线结构后端的切割和芯片封装相互作用故障的损坏

Using crack arrestor for inhibiting damage from dicing and chip packaging interaction failures in back end of line structures
Abstract:
A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep Isolation Trench (UDIT) is cut in the top surface of the chip extending down therein between the perimeter and the barrier. A ILD structure with low-k pSICOH dielectric and hard mask layers is formed over the substrate prior to forming the barrier and the UDIT. The ILD structure interconnection structures can be recessed down to the substrate aside from the UDIT.
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