Invention Grant
- Patent Title: Method of forming stacked die package
- Patent Title (中): 堆叠模包装成型方法
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Application No.: US11957486Application Date: 2007-12-17
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Publication No.: US07955953B2Publication Date: 2011-06-07
- Inventor: Wai Yew Lo , Heng Keong Yip
- Applicant: Wai Yew Lo , Heng Keong Yip
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agent Charles Bergere
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L23/495

Abstract:
A method of packaging semiconductor integrated circuits, including the steps of providing a transfer film and forming a patterned, conductive layer on a surface of the transfer film. A first semiconductor integrated circuit (IC) then is attached to the transfer film, where an active side of the first IC is attached to the transfer film. A second semiconductor IC then is attached to the first IC, where a bottom side of the second IC is attached to a bottom side of the first IC. Die pads on an active surface of the second IC are electrically connected to the conductive layer with wires and then a resin material is provided on one side of the transfer film to encapsulate the first and second ICs, the wires and a portion of the conductive layer. Next the transfer film is removed, which exposes the active side of the first IC and the conductive layer. An electrical distribution layer is formed over the active side of the first IC and the conductive layer and conductive balls are attached to the electrical distribution layer. The conductive balls allow electrical interconnection to the first and second integrated circuits.
Public/Granted literature
- US20090152717A1 METHOD OF FORMING STACKED DIE PACKAGE Public/Granted day:2009-06-18
Information query
IPC分类: