Invention Grant
- Patent Title: Method of manufacturing stacked semiconductor device
- Patent Title (中): 层叠半导体器件的制造方法
-
Application No.: US12508905Application Date: 2009-07-24
-
Publication No.: US07955896B2Publication Date: 2011-06-07
- Inventor: Atsushi Yoshimura , Shoko Omizo
- Applicant: Atsushi Yoshimura , Shoko Omizo
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Turocy & Watson, LLP
- Priority: JP2008-202994 20080806
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
A first semiconductor element is mounted on a wiring board. A second semiconductor element having a portion projecting to an outer side of an outer periphery of the first semiconductor element is disposed on the first semiconductor element via an adhesive. The adhesive has a viscosity (μ0.5 rpm) at a low-rotation speed in a range from 10 Pa·s to 150 Pa·s and a thixotropic ratio of 2 or higher expressed by a ratio (μ0.5 rpm/μ5 rpm) of the viscosity (μ0.5 rpm) at the low-rotation speed to a viscosity (μ5 rpm) at a high-rotation speed. The second semiconductor element is bonded onto the first semiconductor element while the adhesive is filled in a hollow portion between the projecting portion of the second semiconductor element and the wiring board.
Public/Granted literature
- US20100035381A1 METHOD OF MANUFACTURING STACKED SEMICONDUCTOR DEVICE Public/Granted day:2010-02-11
Information query
IPC分类: