Invention Grant
- Patent Title: Structure and method for stacked wafer fabrication
- Patent Title (中): 堆叠晶片制造的结构和方法
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Application No.: US12267244Application Date: 2008-11-07
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Publication No.: US07955895B2Publication Date: 2011-06-07
- Inventor: Ku-Feng Yang , Wen-Chih Chiou , Weng-Jin Wu , Hung-Jung Tu
- Applicant: Ku-Feng Yang , Wen-Chih Chiou , Weng-Jin Wu , Hung-Jung Tu
- Applicant Address: TW Hsin-Chu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsin-Chu
- Agency: Birch, Stewart, Kolasch & Birch, LLP
- Main IPC: H01L21/00
- IPC: H01L21/00

Abstract:
A method for fabricating stacked wafers is provided. In one embodiment, the method comprises providing a wafer having a chip side and a non-chip side, the chip side comprising a plurality of semiconductor chips. A plurality of dies is provided, each of the die bonded to one of the plurality of semiconductor chips. The chip side of the wafer and the plurality of dies are encapsulated with a protecting material. The non-chip side of the wafer is thinned to an intended thickness. The wafer is then diced to separate the wafer into individual semiconductor packages.
Public/Granted literature
- US20100117226A1 STRUCTURE AND METHOD FOR STACKED WAFER FABRICATION Public/Granted day:2010-05-13
Information query
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