Invention Grant
- Patent Title: Techniques for three-dimensional circuit integration
- Patent Title (中): 三维电路集成技术
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Application No.: US12132029Application Date: 2008-06-03
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Publication No.: US07955887B2Publication Date: 2011-06-07
- Inventor: Solomon Assefa , Kuan-Neng Chen , Steven J. Koester , Yurii A. Vlasov
- Applicant: Solomon Assefa , Kuan-Neng Chen , Steven J. Koester , Yurii A. Vlasov
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Michael J. Chang, LLC
- Agent Vazken Alexanian
- Main IPC: H01L21/20
- IPC: H01L21/20

Abstract:
Integrated circuits having complementary metal-oxide semiconductor (CMOS) and photonics circuitry and techniques for three-dimensional integration thereof are provided. In one aspect, a three-dimensional integrated circuit comprises a bottom device layer and a top device layer. The bottom device layer comprises a digital CMOS circuitry layer; and a first bonding oxide layer adjacent to the digital CMOS circuitry layer. The top device layer comprises a substrate; an analog CMOS and photonics circuitry layer formed in a silicon-on-insulator (SOI) layer adjacent to the substrate, the SOI layer having a buried oxide (BOX) with a thickness of greater than or equal to about one micrometer; and a second bonding oxide layer adjacent to a side of the analog CMOS and photonics circuitry layer opposite the substrate. The bottom device layer is bonded to the top device layer by an oxide-to-oxide bond between the first bonding oxide layer and the second bonding oxide layer.
Public/Granted literature
- US20090297091A1 Techniques for Three-Dimensional Circuit Integration Public/Granted day:2009-12-03
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