Invention Grant
- Patent Title: Design Pattern correcting method, process proximity effect correcting method, and semiconductor device manufacturing method
- Patent Title (中): 设计图案校正方法,过程接近效应校正方法和半导体器件制造方法
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Application No.: US12269705Application Date: 2008-11-12
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Publication No.: US07949967B2Publication Date: 2011-05-24
- Inventor: Toshiya Kotani , Shigeki Nojima , Shimon Maeda
- Applicant: Toshiya Kotani , Shigeki Nojima , Shimon Maeda
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.
- Priority: JP2004-134011 20040428
- Main IPC: G06F17/50
- IPC: G06F17/50

Abstract:
A design pattern correcting method of correcting a design pattern in relation to a minute step of the design pattern, is disclosed, which comprises extracting at least one of two edges extended from a vertex of the design pattern, measuring a length of the extracted edge, determining whether or not the length of the measured edge is shorter than a predetermined value, extracting two vertexes connected to the extracted edge if it is determined that the length of the extracted edge is shorter than the predetermined value, and reshaping the design pattern to match positions of the two extracted vertexes with each other.
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