Invention Grant
- Patent Title: Memory system, computer system and memory
- Patent Title (中): 内存系统,计算机系统和内存
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Application No.: US12033311Application Date: 2008-02-19
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Publication No.: US07949852B2Publication Date: 2011-05-24
- Inventor: Shinji Tanaka
- Applicant: Shinji Tanaka
- Applicant Address: JP Osaka-shi
- Assignee: MegaChips Corporation
- Current Assignee: MegaChips Corporation
- Current Assignee Address: JP Osaka-shi
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2007-039387 20070220
- Main IPC: G06F11/22
- IPC: G06F11/22 ; G06F12/00

Abstract:
The correspondence between logical addresses and physical addresses is determined so that the logical addresses in ascending order may be assigned to the physical addresses in ascending order with the physical addresses of defective blocks in a memory skipped. Then, the physical addresses of the defective blocks in ascending order are sequentially stored into the second blocks in ascending order of the physical addresses of the second blocks, respectively. To obtain a physical address from a logical address, a target block is retrieved out of a plurality of second blocks on the basis of the logical address, and the physical address of the target block is added to the logical address to obtain the physical address. Thus, it is possible to reduce the required capacity of a reserve storage region used for conversion of logical addresses into physical addresses without deteriorating the access speed.
Public/Granted literature
- US20080201546A1 MEMORY SYSTEM, COMPUTER SYSTEM AND MEMORY Public/Granted day:2008-08-21
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