Invention Grant
US07941637B2 Groups of serially coupled processor cores propagating memory write packet while maintaining coherency within each group towards a switch coupled to memory partitions
有权
串联耦合的处理器核心组传播存储器写入包，同时保持每个组内的一致性，转向耦合到存储器分区的交换机
- Patent Title: Groups of serially coupled processor cores propagating memory write packet while maintaining coherency within each group towards a switch coupled to memory partitions
- Patent Title (中): 串联耦合的处理器核心组传播存储器写入包，同时保持每个组内的一致性，转向耦合到存储器分区的交换机
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Application No.: US12103250Application Date: 2008-04-15
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Publication No.: US07941637B2Publication Date: 2011-05-10
- Inventor: Perry H. Pelley, III , George P. Hoekstra , Lucio F. C. Pessoa
- Applicant: Perry H. Pelley, III , George P. Hoekstra , Lucio F. C. Pessoa
- Applicant Address: US TX Austin
- Assignee: Freescale Semiconductor, Inc.
- Current Assignee: Freescale Semiconductor, Inc.
- Current Assignee Address: US TX Austin
- Agent James L. Clingan, Jr.; David G. Dolezal
- Main IPC: G06F15/80
- IPC: G06F15/80
Abstract:
A system has a first plurality of cores in a first coherency group. Each core transfers data in packets. The cores are directly coupled serially to form a serial path. The data packets are transferred along the serial path. The serial path is coupled at one end to a packet switch. The packet switch is coupled to a memory. The first plurality of cores and the packet switch are on an integrated circuit. The memory may or may not be on the integrated circuit. In another aspect a second plurality of cores in a second coherency group is coupled to the packet switch. The cores of the first and second pluralities may be reconfigured to form or become part of coherency groups different from the first and second coherency groups.
Public/Granted literature
- US20090259825A1 MULTI-CORE PROCESSING SYSTEM Public/Granted day:2009-10-15
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