A semiconductor memory (2) comprises a controller (21) and a memory array (22). The memory array (22) is controlled for each of block areas (221, 221 . . . ). The information processing apparatus (1) can not generate a data erase command for each block area (221). A data erase command (30) for a specified block area “G” is encoded and stored in a block area “A”. When a request for data erasing is issued, a CPU (11) of the information processing apparatus (1) reads an erase command (30) out from the semiconductor memory (2) and outputs the erase command (30) to the controller (21). The controller (21) decodes the erase command (30) and performs a data erasing process for the block area “G”.