Invention Grant
US07940562B2 Non-volatile semiconductor memory device having non-selected word lines adjacent to selected word lines being charged at different timing for program disturb control
有权
具有与所选字线相邻的未选字线的非易失性半导体存储器件在不同的定时被充电用于程序干扰控制
- Patent Title: Non-volatile semiconductor memory device having non-selected word lines adjacent to selected word lines being charged at different timing for program disturb control
- Patent Title (中): 具有与所选字线相邻的未选字线的非易失性半导体存储器件在不同的定时被充电用于程序干扰控制
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Application No.: US12689786Application Date: 2010-01-19
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Publication No.: US07940562B2Publication Date: 2011-05-10
- Inventor: Hiroshi Nakamura , Tomoharu Tanaka
- Applicant: Hiroshi Nakamura , Tomoharu Tanaka
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2004-120368 20040415; JP2005-013063 20050120
- Main IPC: G11C11/34
- IPC: G11C11/34

Abstract:
A non-volatile semiconductor memory device includes a memory cell array of data-rewritable non-volatile memory cells or memory cell units containing the memory cells, and a plurality of word lines each commonly connected to the memory cells on the same row in the memory cell array. In write pulse applying during data writing, a high voltage for writing is applied to a selected word line, and an intermediate voltage for writing is applied to at least two of non-selected word lines. The beginning of charging a first word line located between the selected word line and a source line to a first intermediate voltage for writing is followed by the beginning of charging a second word line located between the selected word line and a bit line contact to a second intermediate voltage for writing.
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