An integrated circuit is provided comprising an array of memory cells connected by word and bit lines, respectively, wherein each memory cell comprises a thyristor structure, an anode terminal that connects the thyristor structure with a respective bit line, a gate terminal that connects the thyristor structure with a respective word line, and a cathode terminal. The integrated circuit further comprises a drive/sensing circuitry configured to apply a first sequence of voltage signals at the anode terminal and the gate terminal, wherein the voltage signals are defined with respect to the cathode terminal. The first sequence comprises a first voltage signal at the anode terminal, a second voltage signal at the gate terminal, and thereafter a combination of a third voltage signal at the anode terminal and a fourth voltage signal at the gate terminal, wherein the third voltage signal is lower than the first voltage signal and lower than the fourth voltage signal.