Invention Grant
- Patent Title: ROM array
- Patent Title (中): ROM阵列
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Application No.: US12320667Application Date: 2009-01-30
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Publication No.: US07940546B2Publication Date: 2011-05-10
- Inventor: Sriram Thyagarajan , Gus Yeung , Andrew John Sowden
- Applicant: Sriram Thyagarajan , Gus Yeung , Andrew John Sowden
- Applicant Address: GB Cambridge
- Assignee: ARM Limited
- Current Assignee: ARM Limited
- Current Assignee Address: GB Cambridge
- Agency: Nixon & Vanderhye P.C.
- Main IPC: G11C17/00
- IPC: G11C17/00

Abstract:
A ROM array is provided, comprising a plurality of columns of memory cells, wherein each column of memory cells is coupled to a shared bit line which is shared by that column of memory cells and an adjacent column of memory cells. Each column of memory cells has its own associated reference line, which is selectively coupled to a reference potential. Each reference line is coupled to the reference potential when a read operation is performed on a memory cell of the associated column of memory cells. Each reference line is decoupled from the reference potential when a read operation is performed on a memory cell of the adjacent column of memory cells. Both reference lines associated, via their columns of memory cells, to a shared bit line are decoupled from the reference potential when the shared bit line is being pre-charged prior to the read operation. The present invention thus provides a ROM array in which both leakage reduction and speed increase benefits result, whilst providing a high density design.
Public/Granted literature
- US20100195365A1 ROM array Public/Granted day:2010-08-05
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