Invention Grant
- Patent Title: Low power synchronous memory command address scheme
- Patent Title (中): 低功耗同步存储器命令地址方案
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Application No.: US12050950Application Date: 2008-03-19
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Publication No.: US07940543B2Publication Date: 2011-05-10
- Inventor: Chia-Jen Chang , Phat Truong
- Applicant: Chia-Jen Chang , Phat Truong
- Applicant Address: TW Kueishan, Tao-Yuan Hsien
- Assignee: Nanya Technology Corp.
- Current Assignee: Nanya Technology Corp.
- Current Assignee Address: TW Kueishan, Tao-Yuan Hsien
- Agent Winston Hsu; Scott Margo
- Main IPC: G11C5/00
- IPC: G11C5/00 ; G11C7/00
Abstract:
A method for dynamically enabling address receivers in a synchronous memory array includes: controlling all address receivers to initially be in an off state; generating a command signal and generating an address signal; delaying the address signal so there is a latency between the command signal and the address signal; and selectively turning on an address receiver corresponding to the address signal when the command signal is received by the synchronous memory array.
Public/Granted literature
- US20090238014A1 LOW POWER SYNCHRONOUS MEMORY COMMAND ADDRESS SCHEME Public/Granted day:2009-09-24
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