Invention Grant
- Patent Title: Method and apparatus for wafer level burn-in
- Patent Title (中): 晶圆级老化的方法和装置
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Application No.: US12063276Application Date: 2006-05-29
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Publication No.: US07940064B2Publication Date: 2011-05-10
- Inventor: Terutsugu Segawa , Minoru Sanada
- Applicant: Terutsugu Segawa , Minoru Sanada
- Applicant Address: JP Osaka
- Assignee: Panasonic Corporation
- Current Assignee: Panasonic Corporation
- Current Assignee Address: JP Osaka
- Agency: Steptoe & Johnson LLP
- Priority: JP2005-230194 20050809
- International Application: PCT/JP2006/310686 WO 20060529
- International Announcement: WO2007/017981 WO 20070215
- Main IPC: G01R31/00
- IPC: G01R31/00

Abstract:
A temperature regulation plate 106 is divided into at least two areas, a heater 408 for applying a temperature load in correspondence with such areas and its control system are divided and controlled independently to set temperatures, and a cooling source is controlled by comparing the measurements from temperature sensors 409 arranged in respective areas for controlling the heater 408 and switching the measurement for calculating the control output sequentially thus reducing variation in in-plane temperature of a wafer due to heating when an electric load is applied. Since consumption and burning of a probe are prevented, highly reliable wafer level burn-in method and apparatus can be provided.
Public/Granted literature
- US20090102499A1 METHOD AND APPARATUS FOR WAFER LEVEL BURN-IN Public/Granted day:2009-04-23
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