In one embodiment, a metal-semiconductor field effect transistor (MESFET) comprises a first silicon layer, an insulator layer formed on the first silicon layer, and a second silicon layer formed on the insulator layer. A gate region, a source region, and a drain region are formed in the second silicon layer. A first partial trench is formed in the second silicon layer between at least a portion of the gate region and at least a portion of the source region, wherein the first partial trench stops short of the insulator layer. A second partial trench formed in the second silicon layer between at least a portion of the gate region and at least a portion of the drain region, wherein the second partial trench stops short of the insulator layer. First and second oxide spacers are formed in the first and second partial trenches. The first and second oxide spacers and the source region, gate region, and the drain region are substantially planar.