Methods of forming a field effect transistors, pluralities of field effect transistors, and DRAM circuitry comprising a plurality of individual memory cells

Invention Grant

US07939403B2 Methods of forming a field effect transistors, pluralities of field effect transistors, and DRAM circuitry comprising a plurality of individual memory cells 有权

Title translation: 形成场效应晶体管，多个场效应晶体管和包括多个单独存储单元的DRAM电路的方法

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Patent Title: Methods of forming a field effect transistors, pluralities of field effect transistors, and DRAM circuitry comprising a plurality of individual memory cells
Patent Title (中): 形成场效应晶体管，多个场效应晶体管和包括多个单独存储单元的DRAM电路的方法
Application No.: US11601478

Application Date: 2006-11-17
Publication No.: US07939403B2

Publication Date: 2011-05-10
Inventor: Paul Grisham , Gordon A. Haller , Sanh D. Tang
Applicant: Paul Grisham , Gordon A. Haller , Sanh D. Tang
Applicant Address: US ID Boise
Assignee: Micron Technology, Inc.
Current Assignee: Micron Technology, Inc.
Current Assignee Address: US ID Boise
Agency: Wells St. John P.S.
Main IPC: H01L21/8238
IPC: H01L21/8238

Methods of forming a field effect transistors, pluralities of field effect transistors, and DRAM circuitry comprising a plurality of individual memory cells

Abstract:

A method of forming a field effect transistor includes forming trench isolation material within a semiconductor substrate and on opposing sides of a semiconductor material channel region along a length of the channel region. The trench isolation material is formed to comprise opposing insulative projections extending toward one another partially under the channel region along the channel length and with semiconductor material being received over the projections. The trench isolation material is etched to expose opposing sides of the semiconductor material along the channel length. The exposed opposing sides of the semiconductor material are etched along the channel length to form a channel fin projecting upwardly relative to the projections. A gate is formed over a top and opposing sides of the fin along the channel length. Other methods and structures are disclosed.

Abstract(Chinese):

形成场效应晶体管的方法包括在半导体衬底内形成沟槽隔离材料，并在沟道区的长度上在半导体材料沟道区的相对侧上形成沟道隔离材料。沟槽隔离材料形成为包括沿着沟道长度部分地在沟道区域下方朝向彼此延伸的相对的绝缘突起，并且半导体材料被接收在突起上。蚀刻沟槽隔离材料以沿着沟道长度露出半导体材料的相对侧。半导体材料的暴露的相对侧沿通道长度被蚀刻以形成相对于突出部向上突出的通道翅片。栅极沿着沟道长度形成在鳍的顶部和相对侧上。公开了其它方法和结构。

Public/Granted literature

US20080119020A1 Methods of forming a field effect transistors, pluralities of field effect transistors, and DRAM circuitry comprising a plurality of individual memory cells Public/Granted day:2008-05-22

Information query

Espacenet

IPC分类:

H	电学
H01	基本电气元件
H01L	半导体器件；其他类目中不包括的电固体器件（使用半导体器件的测量入G01；一般电阻器入H01C；磁体、电感器、变压器入H01F；一般电容器入H01G；电解型器件入H01G9/00；电池组、蓄电池入H01M；波导管、谐振器或波导型线路入H01P；线路连接器、汇流器入H01R；受激发射器件入H01S；机电谐振器入H03H；扬声器、送话器、留声机拾音器或类似的声机电传感器入H04R；一般电光源入H05B；印刷电路、混合电路、电设备的外壳或结构零部件、电气元件的组件的制造入H05K；在具有特殊应用的电路中使用的半导体器件见应用相关的小类）
H01L21/00	专门适用于制造或处理半导体或固体器件或其部件的方法或设备
H01L21/70	.由在一共用基片内或其上形成的多个固态组件或集成电路组成的器件或其部件的制造或处理；集成电路器件或其特殊部件的制造（由预制电组件组成的组装件的制造入H05K3/00，H05K13/00）
H01L21/77	..在公共衬底中或上面形成的由许多固态元件或集成电路组成的器件的制造或处理（电可编程只读存储器或其多步骤的制造方法入H01L27/115）
H01L21/78	...把衬底连续地分成多个独立的器件（改变表面物理特性或者半导体形状的切割入H01L21/304）
H01L21/82	....制造器件，例如每一个由许多元件组成的集成电路
H01L21/822	.....衬底是采用硅工艺的半导体的（H01L21/8258优先）
H01L21/8232	......场效应工艺
H01L21/8234	.......MIS工艺
H01L21/8238	........互补场效应晶体管，例如CMOS