Invention Grant
- Patent Title: High-voltage SOI MOS device structure and method of fabrication
- Patent Title (中): 高压SOI MOS器件结构及其制造方法
-
Application No.: US12465857Application Date: 2009-05-14
-
Publication No.: US07939395B2Publication Date: 2011-05-10
- Inventor: Wagdi W. Abadeer , Kiran V. Chatty , Robert J. Gauthier, Jr. , Jed H. Rankin , Yun Shi , William R. Tonti
- Applicant: Wagdi W. Abadeer , Lillian Kamal, legal representative , Kiran V. Chatty , Robert J. Gauthier, Jr. , Jed H. Rankin , Yun Shi , William R. Tonti
- Applicant Address: US NY Armonk
- Assignee: International Business Machines Corporation
- Current Assignee: International Business Machines Corporation
- Current Assignee Address: US NY Armonk
- Agency: Roberts Mlotkowski Safran & Cole, P.C.
- Agent Richard Kotulak
- Main IPC: H01L21/336
- IPC: H01L21/336

Abstract:
Structures and methods for integrating a thick oxide high-voltage metal-oxide-semiconductor (MOS) device into a thin oxide silicon-on-insulator (SOI). A method of forming a semiconductor structure includes forming first source and drain regions of a first device below a buried oxide layer of a silicon-on-insulator (SOI) wafer, forming a gate of the first device in a layer of semiconductor material above the buried oxide layer; and forming second source and drain regions of a second device in the layer of semiconductor material above the buried oxide layer.
Public/Granted literature
- US20100289079A1 HIGH-VOLTAGE SOI MOS DEVICE STRUCTURE AND METHOD OF FABRICATION Public/Granted day:2010-11-18
Information query
IPC分类: