Invention Grant
- Patent Title: Method of manufacturing semiconductor element mounted wiring board
- Patent Title (中): 制造半导体元件安装接线板的方法
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Application No.: US12913105Application Date: 2010-10-27
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Publication No.: US07939377B1Publication Date: 2011-05-10
- Inventor: Fumimasa Katagiri , Akihiko Tateiwa
- Applicant: Fumimasa Katagiri , Akihiko Tateiwa
- Applicant Address: JP Nagano-Shi
- Assignee: Shinko Electric Industries Co., Ltd.
- Current Assignee: Shinko Electric Industries Co., Ltd.
- Current Assignee Address: JP Nagano-Shi
- Agency: Kratz, Quintos & Hanson, LLP
- Priority: JP2009-250567 20091030
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H05K1/18

Abstract:
A semiconductor element sealed substrate including a semiconductor element covered by an insulating layer is fabricated while a wiring substrate formed by stacking wiring layers is fabricated by a process different from the process of fabricating the semiconductor element sealed substrate. Next, the semiconductor element sealed substrate and the wiring substrate are stacked on each other in such a way that electrode terminals of the semiconductor element and corresponding conductive bumps on the outermost wiring layer face each other. The electrode terminals and the conductive bumps are thus connected to each other.
Public/Granted literature
- US20110104858A1 METHOD OF MANUFACTURING SEMICONDUCTOR ELEMENT MOUNTED WIRING BOARD Public/Granted day:2011-05-05
Information query
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