Invention Grant
- Patent Title: Method and system for implementing timing analysis and optimization of an electronic design based upon extended regions of analysis
- Patent Title (中): 基于扩展分析区域实现电子设计的时序分析和优化的方法和系统
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Application No.: US11964678Application Date: 2007-12-26
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Publication No.: US07930675B2Publication Date: 2011-04-19
- Inventor: Oleg Levitsky , Kit Lam Cheong , Wilson Chan , Dongzi Liu
- Applicant: Oleg Levitsky , Kit Lam Cheong , Wilson Chan , Dongzi Liu
- Applicant Address: US CA San Jose
- Assignee: Cadence Design Systems, Inc.
- Current Assignee: Cadence Design Systems, Inc.
- Current Assignee Address: US CA San Jose
- Agency: Vista IP Law Group LLP
- Main IPC: G06F17/50
- IPC: G06F17/50 ; G06F9/455

Abstract:
Operations are performed in EDA tools that operate upon partitions or discrete portions of an electronic design, in which the partitions or discrete portions of the design are expanded to account for effects to/from other areas in the design. Identification is made of the portions of the design that are external to the partitions, and depending upon the type of expected effects, would then be considered during optimization and analysis of the partitions. This is implemented by logically expanding the partition to include consideration of the external portions during timing optimization and analysis. By considering an expanded partition for timing optimization and analysis, it is possible to identify unintended problems caused by the timing optimization at an earlier stage of the design process.
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