An integrated circuit for controlling voltage fluctuations. The integrated circuit includes a plurality of clock buffers and latches synchronously operated in accordance with operating clock signals distributed via the clock buffers. The circuit comprises a mechanism for performing an At Speed Test to shift data that are initially set for the latches in accordance with the operating clock signals to succeeding latches, respectively. It also has a timing designation circuit for enabling a clock signal pulse when a first output signal pulse is active. In addition, it includes a ring-type oscillator to consume current in the period during which the first output signal is active. The ring-type oscillator includes a delay control input terminal. The oscillation cycle of the ring-type oscillator is selectively adjusted by adjusting an input of the delay control input terminal.