Invention Grant
- Patent Title: High-speed verifiable semiconductor memory device
- Patent Title (中): 高速可验证半导体存储器件
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Application No.: US12507593Application Date: 2009-07-22
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Publication No.: US07929352B2Publication Date: 2011-04-19
- Inventor: Noboru Shibata
- Applicant: Noboru Shibata
- Applicant Address: JP Tokyo
- Assignee: Kabushiki Kaisha Toshiba
- Current Assignee: Kabushiki Kaisha Toshiba
- Current Assignee Address: JP Tokyo
- Agency: Oblon, Spivak, McClelland, Maier & Neustadt, L.L.P.
- Priority: JP2004-359029 20041210
- Main IPC: G11C16/04
- IPC: G11C16/04

Abstract:
A memory cell stores several data using n (n: natural number more than 1) threshold voltages. A voltage supply circuit supplies a predetermined voltage to a gate of the memory cell in a verify operation of verifying whether or not the memory cell reaches a predetermined threshold voltage. A detection circuit connected to one terminal of the memory cell charges one terminal of the memory cell to a predetermined potential. The detection circuit detects the voltage of one terminal of the memory cell based on a first detection timing, and further, detects the voltage of one terminal of the memory cell based on a second detection timing.
Public/Granted literature
- US20090285029A1 HIGH-SPEED VERIFIABLE SEMICONDUCTOR MEMORY DEVICE Public/Granted day:2009-11-19
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