Integrated circuit and programmable delay. One embodiment provides an integrated circuit including a programmable delay element having a plurality of single delay cells. The delay cells include a first input and a second input and a first output. The delay cells are arranged to form a chain such that the first output of a preceding delay cell is coupled to the second input of a successive delay cell. The first inputs of any delay cells are configured to receive an input signal to be delayed. The delay cells out of the plurality of delay cells is configured to constitute a starting point of a signal path including any of the delay cells arranged downstream of the starting point. The first output of the last delay cell in the chain forms an output of the programmable delay element.