Invention Grant
- Patent Title: Low power consumption MIS semiconductor device
- Patent Title (中): 低功耗MIS半导体器件
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Application No.: US12775976Application Date: 2010-05-07
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Publication No.: US07928759B2Publication Date: 2011-04-19
- Inventor: Hideto Hidaka
- Applicant: Hideto Hidaka
- Applicant Address: JP Kawasaki-shi, Kanagawa
- Assignee: Renesas Electronics Corporation
- Current Assignee: Renesas Electronics Corporation
- Current Assignee Address: JP Kawasaki-shi, Kanagawa
- Agency: Buchanan Ingersoll & Rooney PC
- Priority: JP2002-311029 20021025
- Main IPC: G05F1/10
- IPC: G05F1/10 ; G05F3/02

Abstract:
A logic gate is constructed of an insulated gate field effect transistor (MIS transistor) having a thin gate insulation film. An operation power supply line to the logic gate is provided with an MIS transistor having a thick gate insulation film for switching the supply and stop of an operation power source voltage. A voltage of the gate of the power source switching transistor is made changing in an amplitude greater than an amplitude of an input and an output signal to the logic gate. Current consumption in a semiconductor device configured of MIS transistor of a thin gate insulation film can be reduced and an power source voltage thereof can be stabilized.
Public/Granted literature
- US20100219857A1 LOW POWER CONSUMPTION MIS SEMICONDUCTOR DEVICE Public/Granted day:2010-09-02
Information query
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